GDB Server

The J-Link GDB Server is a remote server for the GDB which allows to use J-Link with GDB or any toolchain which uses GDB as debugging interface, such as Yagarto and Sourcery G++). The GDB and GDB Server communicate via a TCP/IP connection, using the standard GDB remote serial protocol. The GDB supports a standard set of commands like open elf/bin files, reading/writing memory, etc. Beside this, the GDB also supports so called monitor commands which are passed to the GDB Server and interpreted by it, allowing it to implement J-Link specific commands like reading/writing CP15 registers, enabling flash download via J-Link, using flash breakpoints, enabling semihosting, etc.

GNU Project Debugger (GDB) overview

The GNU Project Debugger (GDB) is a freely available debugger, distributed under the terms of the GNU Public license (GPL). It connects to an emulator via a TCP/IP connection. It can connect to every emulator for which a GDB server software is available. The latest Unix version of the GDB is freely available from the GNU commitee under: http://www.gnu.org/software/gdb/download/

GDB Server licensing

J-Link GDB Server is distributed as "free for evaluation and non commercial use". The software can be used free of charge for educational and non-profit purposes without an additional license. To use the software for other, especially commercial purposes, a license is required. To obtain an trial or unlimited license, please このメールアドレスはスパムボットから保護されています。閲覧するにはJavaScriptを有効にする必要があります。 with us. Full and valid license terms are specified in file License.txt which comes with the J-Link software and documentation package.

Note: J-Link OEM versions ATMEL SAM-ICE and Digi JTAG Link come with a built-in license for J-Link GDB Server.

Supported cores

Currently the J-Link GDB Server can be used with the following CPU cores:

• ARM7TDMI (Rev 1)
• ARM7TDMI (Rev 3)
• ARM7TDMI-S (Rev 4)
• ARM720T
• ARM920T
• ARM922T
• ARM926EJ-S
• ARM946E-S
• ARM966E-S
• ARM1136JF-S
• ARM1136J-S
• ARM1156T2-S
• ARM1156T2F-S
• ARM1176JZ-S
• ARM1176JZF
• ARM1176JZF-S
• Cortex-M0
• Cortex-M1
• Cortex-M3

Requirements

To use the J-Link GDB Server, you have to meet the following requirements:

• J-Link / J-Trace ARM / J-Trace for Cortex-M3
• PC running Microsoft Windows 2000 / 2003 / XP / Vista / Windows 7
• Target hardware with ARM / Cortex core

User interface

The J-Link GDB Server's user interface shows information about the debugging process and allows the user to configure some settings like target endianess, if memory reads should be cached in order to improve performance or if a logfile shall be generated.

Setting up the J-Link GDB Server

Typically, most of the GDB and target setup is done from GDB via remote commands (monitor) in the .gdbinit file. The commands used in the .gdbinit file are performed before the download of the application into the target memory is performed. This allows the user to perform initialization steps which might be necessary to enable the access to the target memory. The .gdbinit file also allows to use download into flash memory via J-Link and flash breakpoints.

Protocol extensions

• SWO support
  GDB Server supports transfer of SWO data (terminal output, instrumentation trace, PC samples, etc.)
• ETM (processor trace) support: upon request

J-Link IDE integration

J-Link / J-Trace can be used with different IDEs. Some IDEs support J-Link directly, for other ones additional software (such as J-Link RDI) is necessary in order to use JLink. The following tables list which features of J-Link / J-Trace can be used with the different IDEs.

ARM Cortex-M3
IDE	Debug support4	Flash Download	Flash Breakpoints	Trace support	SWO support
IAR EWARM
Keil MDK
Rowley
CodeSourcery
Yargato (GDB)

ARM7/9
IDE	Debug Support4	Flash Download	Flash Breakpoints	Trace support3
IAR EWARM
Keil MDK
Rowley
CodeSourcery
Yargato (GDB)
RDI compliant toolchains such as RVDS/ADS	1	1	1

ARM11
IDE	Debug support4	Flash Download	Flash Breakpoints	Trace support3
IAR EWARM		2	2
Rowley
Yargato (GDB)		2	2

¹ Requires J-Link RDI license for download of more than 32KBytes

² Coming soon

³ Requires emulator with trace support

⁴ Debug support includes the following: Download to RAM, memory read/write, CPU register read/write,
Run control (go, step, halt), software breakpoints in RAM and hardware breakpoints in flash memory.

Interface description

JTAG interface connection (20 pin)

There is a standard 20 pin connector defined by ARM. J-Link has a built-in 20-pin JTAG connector, which is compatible with this standard.
JTAG interface connector signals:

Notes

All pins marked NC are not connected inside J-Link. Any signal can be applied here; J-Link will simply ignore such a signal.
Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system.

Pin 2 is not connected inside J-Link. A lot of targets have pin 1 and pin 2 connected. Some targets use pin 2 instead of pin 1 to supply VCC. These targets will not work with J-Link, unless Pin 1 and Pin 2 are connected on the target's JTAG connector.

Pin 3 (TRST) should be connected to target CPUs TRST pin (sometimes called NTRST). J-Link will also work if this pin is not connected, but you may experience some limitations when debugging. TRST should be separate from the CPU Reset (pin 15)

Pin 11 (RTCK) should be connected to RTCK if available, otherwise to GND.

Pin 19 (5V-Target supply) of the connector can be used to supply power to the target hardware. Supply volatage is 5V, max. current is 300mA. The output current is monitored and protected agains overload and short-circuit.

SWD and SWO/SWV (also called SWV) compability

SWD overview

The J-Link and J-Trace support ARMs Serial Wire Debug (SWD). SWD replaces the 5-pin JTAG port with a clock (SWDCLK) and a single bi-directional data pin (SWDIO), providing all the normal JTAG debug and test functionality. SWDIO and SWCLK are overlaid on the TMS and TCK pins. In order to communicate with a SWD device, J-Link sends out data on SWDIO, syn- chronous to the SWCLK. With every rising edge of SWCLK, one bit of data is trans- mitted or received on the SWDIO. The data read from SWDIO can than be retrieved from the input buffer.

SWD connector pinout

The following table shows the SWD pinout:

Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system.

Serial Wire Output (SWO) overview

J-Link can be used with devices that supports Serial Wire Output (SWO). Serial Wire Output (SWO) support means support for a single pin output signal from the core. It is currently tested with Cortex-M3 only.

Supported SWO speeds

The supported SWO speeds depend on the connected emulator. They can be retrieved from the emulator. Currently, the following are supported:

Serial Wire Viewer (SWV) overview

The Instrumentation Trace Macrocell (ITM) and Serial Wire Output (SWO) can be used to form a Serial Wire Viewer (SWV). The Serial Wire Viewer provides a low cost method of obtaining information from inside the MCU. The SWO can output trace data in two output formats, but only one output mechanism is valid at any one time. The 2 defined encodings are UART and Manchester. The current J-Link implementation sup- ports only UART encoding. Serial Wire Viewer uses the SWO pin to transmit different packets for different types of information. The three sources in the Cortex-M3 core which can output information via this pin are:

• Instrumentation Trace Macrocell (ITM) for application-driven trace source that supports printf-style debugging. It supports 32 different channels, which allow it to be used for other purposes such as real-time kernel information as well.
• Data Watchpoint and Trace (DWT) for real-time variable monitoring and PC-sampling, which can in turn be used to periodically output the PC or various CPU-internal counters, which can be used to obtain profiling information from the target.
• Timestamping. Timestamps are emitted relative to packets.

Further application documents

Refer to the following documents for detailed information about SWO/SWV:

J-Flash

Documentation download Software download

Programming speeds

The following table shows some performance values regarding the programming speed.

What is multi-bank programming support?

Multi-bank programming support describes the possibility to program different flash devices, present on the same hardware, in one Flash programming session. For example, if you want to use the internal flash of your target hardware as well as the external flash for the target application code, multi-bank programming enables you to download the target application into the internal and external flash in one flash programming session. The settings for both flash banks are saved in the same J-Flash project, so you will only need one project in order to program multiple flash banks.

Support for Atmel DataFlash, NAND flash, SPI-NOR flash

Since the connection of these flashes varies from microcontroller to microcontroller, there are always some modifications which are necessary, to get DataFlash/NAND/SPI-NOR flash supported on a specific hardware.
The J-Flash software comes with sample projects which allow programming the DataFlash/NAND flash on popular eval boards. If you have a hardware-design which is based on the one of the eval board, these sample projects should also work for your custom hardware.
If your hardware design varies too much, usually a custom RAMCode is needed which programs the flash of your target hardware. RAMCodes for custom hardware can be created on request. For more information about pricing and requirements for a custom RAMCode, please contact このメールアドレスはスパムボットから保護されています。閲覧するにはJavaScriptを有効にする必要があります。 . SEGGER also provides a RAMCode template which enables customers to write a custom RAMCode on their own. The RAMCode template is available このメールアドレスはスパムボットから保護されています。閲覧するにはJavaScriptを有効にする必要があります。 .